The present invention is related in general to the field of semiconductor devices and processes and more specifically to a method for chemically reworking metal layer misprocessed on bond pads of integrated circuits having copper metallization.
In integrated circuits (IC) technology, pure or doped aluminum has been the metallization of choice for interconnection and bond pads for more than four decades. Main advantages of aluminum include ease of deposition and patterning. Further, the technology of bonding wires made of gold, copper, or aluminum to the aluminum bond pads has been developed to a high level of automation, miniaturization, and reliability. Examples of the high technical standard of wire bonding to aluminum can be found in U.S. Pat. No. 5,455,195, issued on Oct. 3, 1995 (Ramsey et al., xe2x80x9cMethod for Obtaining Metallurgical Stability in Integrated Circuit Conductive Bondsxe2x80x9d); U.S. Pat. No. 5,244,140, issued on Sep. 14, 1993 (Ramsey et al., xe2x80x9cUltrasonic Bonding Process Beyond 125 kHzxe2x80x9d); U.S. Pat. No. 5,201,454, issued on Apr. 13, 1993 (Alfaro et al., xe2x80x9cProcess for Enhanced Intermetallic Growth in IC Interconnectionsxe2x80x9d); and U.S. Pat No. 5,023,697, issued on Jun. 11, 1991 (Tsumura, xe2x80x9cSemiconductor Device with Copper Wire Ball Bondingxe2x80x9d).
In the continuing trend to miniaturize the ICs, the RC time constant of the interconnection between active circuit elements increasingly dominates the achievable IC speed-power product. Consequently, the relatively high resistivity of the interconnecting aluminum now appears inferior to the lower resistivity of metals such as copper. Further, the pronounced sensitivity of aluminum to electromigration is becoming a serious obstacle. Consequently, there is now a strong drive in the semiconductor industry to employ copper as the preferred interconnecting metal, based on its higher electrical conductivity and lower electromigration sensitivity. From the standpoint of the mature aluminum interconnection technology, however, this shift to copper is a significant technological challenge.
Copper has to be shielded from diffusing into the silicon base material of the ICs in order to protect the circuits from the carrier lifetime-killing characteristic of copper atoms positioned in the silicon lattice. For bond pads made of copper, the formation of thin copper(I)oxide films during the manufacturing process flow has to be prevented, since these films severely inhibit reliable attachment of bonding wires, especially for conventional gold-wire ball bonding. In contrast to aluminum oxide films overlying metallic aluminum, copper oxide films overlying metallic copper cannot easily be broken by a combination of thermocompression and ultrasonic energy applied in the bonding process. As further difficulty, bare copper bond pads are susceptible to corrosion.
In order to overcome these problems, a process has been disclosed to cap the clean copper bond pad with a layer of aluminum and thus re-construct the traditional situation of an aluminum pad to be bonded by conventional gold-wire ball bonding. A suitable bonding process is described in U.S. Pat. No. 5,785,236, issued on Jul. 28, 1998 (Cheung et al., xe2x80x9cAdvanced Copper Interconnect System that is Compatible with Existing IC Wire Bonding Technologyxe2x80x9d). The described approach, however, has several shortcomings.
First, the fabrication cost of the aluminum cap is higher than desired, since the process requires additional steps for depositing metal, patterning, etching, and cleaning. Second, the cap must be thick enough to prevent copper from diffusing through the cap metal and possibly poisoning the IC transistors. Third, the aluminum used for the cap is soft and thus gets severely damaged by the markings of the multiprobe contacts in electrical testing. This damage, in turn, becomes so dominant in the ever decreasing size of the bond pads that the subsequent ball bond attachment is no longer reliable.
A low-cost structure and method for capping the copper bond pads of copper-metallized ICs has been disclosed on U.S. Patent Application No. 60/183,405, filed on Feb. 18, 2000. The present invention is related to that application. The structure provides a metal layer electrolessly plated onto the copper, which impedes the up-diffusion of copper. Of several possibilities, nickel is a preferred choice. This layer is topped by a bondable metal layer, which also impedes the up-diffusion of the barrier metal. Of several possibilities, gold is a preferred choice. In a variation of this sequence of metal layers, a second barrier layer such as palladium is electrolessly deposited on the nickel, blocking its up-diffusion, and then followed by a bondable metal such as gold. Metallurgical connections to the stacked cap of layers can then be performed by conventional wire bonding.
It is difficult, though, to plate these bond pad caps uniformly in electroless deposition systems, because electroless deposition is affected by local reactant concentrations and by the agitation velocities of the aqueous solution. Deposition depletes the reactants in areas around the bond pads. Increasing the agitation of the solution only exacerbates the deposition non-uniformity, which is influenced by the flow direction of the solution. Also, a few bond pads may not receive any metal deposition. The problem is further complicated when a whole batch of wafers is to be plated simultaneously in order to reduce cost, since known control methods have been applied only to process single wafers under applied electrical bias. See, for example, U.S. Pat. No. 5,024,746, issued Jun. 18, 1991, and U.S. Pat. No. 4,931,149, issued Jun. 5, 1990 (Stierman et al., xe2x80x9cFixture and a Method for Plating Contact Bumps for Integrated Circuitsxe2x80x9d).
An urgent need has arisen for a reliable method of reworking metal caps over copper bond pads which combines minimum fabrication cost with maximum correction control of the IC structure. The reworking method should be flexible enough to be applied for different IC product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished while shortening production cycle time and increasing throughput, and without the need of expensive additional manufacturing equipment.
The present invention discloses a method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using selective etchants consecutively until the metal layers over the bond pads are removed without damaging the copper metallization. Replacement metal layers are finally deposited over the bond pads.
The present invention is related to high density and high speed ICs with copper interconnecting metallization, especially those having high numbers of metallized inputs/outputs, or xe2x80x9cbond padsxe2x80x9d. These circuits can be found in many device families such as processors, digital and analog devices, logic devices, high frequency and high power devices, and in both large and small area chip categories.
It is an aspect of the present invention to increase the process yield of wafer fabrication, since it provides a low-cost rework method for wafers misprocessed almost at the end of the process flow. It is towards the completion of the fabrication process when a high amount of work and time has already been invested and the wafers represent high value.
Another aspect of the invention is to support technologies applicable to bond pad area reduction and thus the shrinking of IC chips. Consequently, the invention helps to alleviate the space constraint of continually shrinking applications such as cellular communication, pagers, hard disk drives, laptop computers and medical instrumentation.
Another aspect of the invention is to support the fabrication of bond pad metal caps by the self-defining process of electroless deposition, which is preferable over costly photolithographic and alignment techniques.
Another aspect of the invention is to help advance the process and reliability of wafer-level multi-probing by eliminating probe marks and subsequent bonding difficulties.
Another aspect of the invention is to provide materials and process concepts which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several generations of products.
Another aspect of the invention is to use only materials and processes most commonly employed and accepted in the fabrication of advanced IC devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
These aspects have been achieved by the teachings of the invention concerning selection criteria and process flows suitable for mass production. Various modifications have been successfully employed to satisfy different selections of bonding technologies.
In the first embodiment of the invention, a cyclic dithio-oxamine compound, dissolved for instance in tetra-hydro-furane or acetone, is used as a specific etchant to remove the bondable metal layer, usually gold. The preferred compound is epta-methyl-bis-diiodine, or the bis-diiodine adduct of N,Nxe2x80x2-dimethylperhydrodiazepine-2,3- dithione.
In the second embodiment of the invention, mixtures of inorganic and organic oxidizing acids are used as specific etchants for removing the barrier metal layer/layers. Dependent on the barrier metals (such as nickel and palladium), the acids are selected from a group consisting of hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, acetic acid, and hydrogen peroxide and others.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.